Angeled edge connections for multichip structures

ABSTRACT

A multichip module that utilizes an angled interconnect to electrically interconnect chips in the module that are positioned at an angle relative to each other. The multichip module may comprise a first and second chips that are positioned in an orthogonal manner. The first and second chips are electrically interconnected via an interconnect structure comprising a first conductive pillar that extends from an outer surface of the first chip. A distal end of the first pillar is electrically connected to an outer surface of the second chip via a solder ball or another conductive pillar that is interposed between the distal end of the first conductive pillar and the second chip.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to multichip structures and, inparticular, to chip interconnections in multichip structures.

[0003] 2. Description of the Related Art

[0004] Semiconductor manufacturers continually strive to increase thepackaging density of integrated circuit chips, which has led to thedevelopment of high density multichip modules, such as three-dimensionalmultichip structures. Multichip structures generally comprise aplurality of integrated circuit chips that are adhered together in astack formation so as to reduce the amount of space that the chipsoccupy inside a system. It is generally understood that each chip in thestack typically has a plurality of conductive input/output (I/O)contacts that are exposed on a lateral surface of at least one edge ofthe chip. The exposed contacts provide a plurality of conductive I/Ointerconnects for wire bonding the device to external chips andcircuitry.

[0005] As a result of the increased device density of VLSI(Very-Large-Scale Integration) and ULSI (Ultra-Large-Scale Integration)integrated circuitry, wiring conductive interconnects betweeninput/output (I.O.) terminals of stacked integrated circuit chips hasbecome increasingly more complex. The limitations brought about by thefinite quantity of available space on the surface of a multichipstructure and the levels of conductive traces that are required to wirecomplex integrated circuitry, such as microprocessors, memory modules,etc., has limited the interconnectivity between chips in multichipstructures that require high-density conductive I/O interconnects.

[0006] One method of interconnecting chips within multichip structuresis through the use of the generally known process of wire bonding. TheI/O interconnection process of wire bonding often requires the formationof bondable wire bonding pads, which provide electrical contacts to I/Ovias in the insulation layer of an integrated circuit chip.Unfortunately, bondable wire bonding pads may be relatively large. Inaddition, the available space on a substrate surface for surfacemounting conductive I/O interconnects is limited by the finitedimensions of the device. As a result, the disadvantage to wire bondingas a method of I/O interconnection between integrated circuit chips isthat the bonding pads consume a large amount of the available space onthe integrated circuit chip surface. Therefore, the fabrication densityis limited by the dimensions of the wire bonding pad and further by thefinite dimensions of the integrated circuit chip surface. To furtherincrease the fabrication density of integrated circuitry, amanufacturing process that reduces the need for wire bonding as a meansfor establishing a conductive link between I/O interconnects would bepreferred.

[0007] In another aspect, integrated circuits chips within a multichipstructure may be interconnected by a direct solderable C4 connection,but the I/O interconnection surfaces are usually limited to an opposedparallel positioning of the integrated circuit chips. An opposingparallel position refers to a chip configuration where the bondingelements are interposed between two parallel bonding plane surfaces oftwo opposing chips, which is similar to a sandwich configuration.Disadvantageously, the opposing parallel configuration reducesinterconnection and mounting flexibility and can only be applied toparallel oriented chips in multichip structures, which is likely toreduce the available I/O interconnect density for chips that are notparallel and adjacent to one another.

[0008] Hence, it will be appreciated that there is a need for a methodof increasing the interconnect density and interconnection flexibilitybetween chips in multichip modules. There is also a need for a method ofelectrically connecting chips that are not positioned in an opposingparallel fashion. To this end, there is a particular need for amultichip structure that provides an increased interconnect density andflexibility between chips that are not positioned parallel to oneanother.

SUMMARY OF THE INVENTION

[0009] In one aspect, the preferred embodiments of the present inventiondisclose an integrated circuit module comprising a first semiconductorstructure having a first surface defined by a first plane and a secondsemiconductor structure having a second surface defined by a secondplane, wherein the second structure is positioned adjacent the firststructure in a manner such that the second plane intersects the firstplane. The module further comprises a first connecting member extendingfrom the first surface of first structure. Preferably, the firstconnecting member has a first distal end that is electrically connectedto the first surface and a second distal end extending from the firstsurface along a first axis.

[0010] Preferably, the module also comprises a second connecting memberthat is interposed between the second distal end of the first connectingmember and the second surface of the second structure, wherein thesecond connecting member electrically interconnects the second distalend to the second surface and forms a bond therebetween along a secondaxis. Preferably, the second axis is not parallel to the first axis. Inone embodiment, the first connecting member comprises a conductivepillar and the second connecting member comprises a solder ball. Inanother embodiment, both the first and second connecting memberscomprise conductive pillars and the conductive pillars may be joinedtogether via solder.

[0011] In another aspect, the preferred embodiments of the presentinvention disclose a multichip module comprising a plurality ofsemiconductor chips stacked and secured together to form a basestructure wherein the base structure has a first and a second lateralface, wherein each lateral face is comprised of a portion of each chip,wherein the first lateral face is adjacent to and substantiallyperpendicular to the second lateral face. The module further comprises afirst exterior semiconductor chip mounted to the first lateral face ofthe base structure in a manner such that a first surface of the firstexterior chip is positioned adjacent to the first lateral face andextends across at least a portion of the first lateral face. Preferably,the module also comprises a second exterior semiconductor chip mountedto the second lateral face of the base structure in a manner such that afirst surface of the second exterior chip is positioned adjacent to thesecond lateral face and extends across at least a portion of the secondlateral face. The first and second exterior chips are electricallyconnected via a connecting member. Preferably, the connecting membercomprises a first distal end that is electrically connected to the firstsurface of the first exterior chip and a second distal end that iselectrically connected to the first surface of the second exterior chip.In one embodiment, the connecting member comprises a conductive pillar.A solder ball is preferably interposed between the second distal end ofthe connecting member and the first surface of the second semiconductorchip. In another embodiment, the first distal end of the connectingmember extends along a first axis and the second distal end extendsalong a second axis, wherein the first axis and the second axis arenon-parallel.

[0012] In yet another aspect, the preferred embodiments of the presentinvention is directed to a method of forming electrical interconnectionsbetween two integrate circuit structures. The method comprises forming afirst conductive contact on a first surface of a first semiconductorchip and a second conductive contact on a second surface of a secondsemiconductor chip. The method further comprises forming a connectingmember on the first contact wherein a distal end of the connectingmember extends from the first surface of the first semiconductor chip.The method further comprises positioning the chips in a manner such thatthe plane defining the first surface intersects with plane the definingthe second surface. Furthermore, the method comprises affixing thedistal end of the connecting member to the second contact of the secondchip to electrically connect the first and second semiconductor chips.In one embodiment, the distal end can be affixed to the second contactby interposing either a solder ball or a conductive pillar between thedistal end and the second contact. In another embodiment, the conductivepillar can be formed by a selective CVD, electroless plating,electroplating, or a blanket deposition using a tape lift-off process.In yet another embodiment, the solder ball can be formed via a selectiveimmersion, tape liftoff, or metal mask process and then reflowed in H₂.

[0013] Advantageously, the preferred embodiments of the presentinvention provide an increased interconnection flexibility betweenintegrated circuit chips. In particular, densely packed multichipstructures may be mounted and interconnected at an angular offset fromeach other, which also allows for a reduction of unused space within thestructure and an adaptation to irregular shaped configurations. Withincreased interconnection flexibility, multichip structures may utilizea greater area of surface space for multichip interconnectivity and thusincrease the interconnect density. The increased interconnectflexibility and density may result in an increase in speed of themultichip structure due to the increase in available I/Ointerconnections and a reduced conductive trace length between multiplechip I/O interconnections. These and other advantages of the presentinvention will become more fully apparent from the following descriptiontaken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 provides a schematic illustration of a multichip structureof the preferred embodiment, showing the chips positioned at asubstantially orthogonal angle and interconnected using the preferredinterconnection method;

[0015]FIG. 2 provides a schematic illustration of another preferredembodiment of a multichip structure, showing the chips positioned at anacute angle and interconnected using the preferred interconnectionmethod;

[0016]FIG. 3 provides a schematic illustration of another embodiment ofthe multichip structure of FIG. 1, showing another embodiment of theinterconnection method;

[0017]FIG. 4 illustrates a schematic illustration of yet anotherembodiment of a multichip structure, showing three chips interconnectedto each other using one embodiment of the preferred interconnectionmethod;

[0018]FIG. 5 illustrates a schematic illustration of one embodiment of athree-dimensional multichip module utilizing one embodiment of thepreferred interconnection method;

[0019]FIG. 6 illustrates a cross-sectional view of the three-dimensionalmultichip module in FIG. 5 taken along the line 6-6.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0020] References will now be made to the drawings wherein like numeralsrefer to like parts throughout. FIG. 1 illustrates a multichip structure110 of a preferred embodiment. The multichip structure 110 comprises afirst integrated circuit chip 111 having a first surface 116 a and asecond integrated circuit chip 112 having a second surface 116 b. Asshown in FIG. 1, the chips 111, 112 are positioned in a manner such thatthe first surface 116 a is substantially adjacent and orthogonal to thesecond surface 116 b. As FIG. 1 further shows, a first conductivecontact 115 a is formed on the first chip 111 and a first connectingmember 113 extends from the first contact 115 a. Preferably, a secondconductive contact 115 b is also formed on the second chip 112 and asecond connecting member 114 is interposed between the first connectingmember 113 and the second contact 115 b so as to establish electricalinterconnection therebetween. Particularly, the first connecting member113 has a first distal end 118 a that is attached to the first contact115 a and a second distal end 118 b that extends from the first surface116 a along a first axis. The second connecting member 114 is preferablyinterposed between the second distal end 118 b and the second contact115 b so as to form a conductive bond therebetween. Preferably, the bondis formed along a second axis that is not parallel to the first axis.

[0021] In one embodiment, the first connecting member 113 is aconductive pillar comprising a conductive material, such as copper,while the second connecting member 114 may be a generally known solderball used in C4 interconnections. In one embodiment, the solder ball 114may be first formed on the second distal end 118 b of the firstconnecting member 113 and then bonded to the second contact 115 b on thesecond surface 116 b. In another embodiment, the solder ball 114 may befirst formed on the second contact 115 b and then bonded to the seconddistal end 118 b of the first connecting member 113. The advantage tousing the conductive pillar 113 in conjunction with the solder ball 114is that an angular conductive interconnection may be established betweentwo semiconductor structures, such as the first and second chips 111,112. Therefore, conductive interconnection between chips is not limitedto chips positioned in an opposing parallel position.

[0022] As shown in FIG. 1, the first and second connecting members 113,114 are joined together to electrically interconnect the chips 111, 112.In one embodiment, the first and second chips 111, 112 may compriseelectrical devices such as logic gates, memory modules, capacitors,resistors, and the like. In another embodiment, the first and secondchips 111, 112 may be replaced with insulator based wafers comprising aplurality of conductive traces for interconnection of electricalcomponents between integrated circuit chips.

[0023] A preferred process for the fabrication of the multichipstructure 110 shown in FIG. 1 may proceed as follows. The first andsecond chips 111, 112 are fabricated in accordance with conventionalintegrated circuit manufacturing processes. After the completion of thenext to last layer of chip metallurgy, an insulating layer is depositedon the first and second chips 111, 112 and planarized using methods thatare known in the art. A solderable metallurgy layer is then deposited onthe insulating layer and photo processed to form the last level ofconductive traces and/or conductive contact points. Preferably, theconductive contact points comprise the first and second conductivecontacts 115 a, 115 b as shown in FIG. 1. In one embodiment, thecontacts 115 a, 115 b comprise conductive pads that provide electricalinterconnection to internal circuitry in the chips. Subsequent toforming the conductive contacts 115 a, 115 b, the conductive pillar 113may be formed on the first contact 115 a using selective CVD,electroless plating, electroplating or a blanket deposition inconjunction with a known tape life-off process. Similarly, the solderball 114 may be formed on the second exposed contact 115 b usinggenerally known C4 (Controlled Collapsed Chip Connection) processes, inwhich a lift-off procedure is used to form the solder ball.Alternatively, the solder ball 114 may be formed on the second distalend 118 b of the first connecting member 113 using several differentknown methods such as selective immersion, tape lift-off, or metal maskto deposit solder. In one embodiment, the process continues by reflowingthe solder in H₂ to form a solder ball 114. The multichip module 110 maybe subsequently mounted to an appropriate substrate, which may be theouter surface of a multichip stacked module as will be discussed furtherbelow.

[0024]FIG. 2 illustrates another embodiment of a multichip structure 210showing a second chip 212 positioned at an angular offset 217 from afirst chip 211. In this embodiment, the angle 217 formed between the twochips 211, 212 is less than 90 degrees, however, it can be appreciatedthat this angle can vary without departing from the scope of theinvention. In another embodiment, for example, the angle 217 may begreater than 90 degrees. As shown in FIG. 2, a conductiveinterconnection 221 between the two chips 211, 212 is achieved in asimilar manner as the interconnection 121 illustrated in FIG. 1. Similarto the module illustrated in FIG. 1, the conductive interconnection 221comprises a first connecting member 213 which extends from a firstcontact 215 a formed on the first chip. A second connecting member 214,which preferably comprises a solder ball, is interposed between thefirst connecting member and a second contact formed on the second chip212. As illustrated in FIG. 2, if it is desired to attach the chips 211,212 at an angular offset other than orthogonal as in FIG. 1, the sameprocedures may be used as in FIG. 1 except that the chips would bepositioned at the desired angle prior to attaching the first connectingmember to the second connecting member. These connections are especiallyuseful in complex multichip stack modules, which will be discussed infurther detail below. It should also be apparent to one skilled in theart that these connections can be adapted to structures using generallyknown C4 connections so that the contact between the chips may besecured at various angles.

[0025]FIG. 3 illustrates yet another embodiment of a multichip structure310. In this embodiment, the multichip structure 310 comprises a secondconnecting member 313 b that is also a conductive pillar having a firstdistal end 319 a and a second distal end 319 b. The first distal end 319a is attached to a second exposed contact 315 b formed a second surface316 b of the second chip 312. Preferably, the second distal end 319 bextends from the second surface 316 b along an axis that issubstantially orthogonal to the first connecting member 313 a. Thesecond distal end 319 b of the second connecting member 313 b ispositioned adjacent to the second distal end 318 b of the firstconnecting member 313 a. Furthermore, a conductive bonding element 320such as solder is used to electrically interconnect the second distalends 318 b, 319 b of the connecting members 313 a, 313 b. The advantageto this particular embodiment is increased orientation flexibility,where the positioning of the first and second chips 311, 312 may formvarious angular displacements between the two chips 311, 312 withoutdeparting from the scope of the invention.

[0026]FIG. 4 illustrates still another embodiment of a multichipstructure 410. The multichip structure 410 further includes a third chip423. The third chip 423 is positioned substantially parallel to thesecond chip 412 and interconnected to the second chip 412 by way of aplurality of conductive interconnects 425. In one embodiment, theconductive interconnects 425 comprise conventional C4 solderconnections. This particular embodiment illustrates the angular mountingof chips 411, 412 substantially orthogonal to each other via theconductive interconnection 421 described above and the simultaneousmounting of chips 412, 423 substantially parallel to each other via theconductive interconnection 425. The advantage to multiple chip mountingorientations is that chip interconnection density may be increased dueto an increase in the chip mounting flexibility between chips 411, 412,423. The advantage to this chip mounting configuration is that aplurality of planar structures may be simultaneously mounted in bothangular and parallel configurations in one multichip structure.

[0027]FIG. 5 illustrates one embodiment of a three-dimensional multichipmodule 550, which utilizes the interconnection methods described aboveto interconnect the exterior chips of the module. As FIG. 5 shows, themultichip module 550 comprises a plurality of semiconductor chips 520stacked and secured together to form a base structure 525, wherein thebase structure has four lateral faces 530 a-d (only one is shown).Preferably, each lateral face 530 is comprised of a portion of eachchip. Preferably, a first lateral face 530 a is adjacent to andsubstantially perpendicular to a second lateral face 530 b, while athird lateral face 530 c is adjacent to and substantially perpendicularto the second face 530 b. As FIG. 5 shows, a first exteriorsemiconductor chip 562 is mounted to the first lateral face 530 a of thebase structure 525 in a manner such that a first surface (not shown) ofthe first exterior chip 562 is positioned adjacent to the first lateralface 530 a and extends across at least a portion of the first lateralface 530 a. Furthermore, a second exterior semiconductor chip 561 ismounted to the second lateral face 530 b of the base structure 525 in amanner such that a first surface (not shown) of the second exterior chip561 is positioned adjacent to the second lateral face 530 b and extendsacross at least a portion of the second lateral face. Similarly, a thirdexterior chip 560 is mounted to the third lateral face 530 c of the basestructure 525 in a manner such that a first surface (not shown) of thethird exterior chip 560 is positioned adjacent to the third lateral face530 c and extends across at least a portion of the third lateral face530 c. The multichip module 550 is described in detail in Applicant'sco-pending U.S. patent application entitled “A THREE-DIMENSIONALMULTICHIP MODULE AND METHOD OF MAKING THE SAME”, which is incorporatedby reference herein in its entirety.

[0028]FIG. 6 illustrates a cross-sectional view taken along the line 6-6of the three-dimensional multichip module 550 shown in FIG. 5. FIG. 6shows the three exterior chips 560, 561, 562 are interconnected witheach other using conductive interconnects 521, 525, 527 of the preferredembodiments shown and described above in detail in FIGS. 1-4. As shownin FIG. 6, the exterior chips 560, 561, 562 are mounted in parallel withthe exterior faces of the base structure 525 through the plurality ofconductive interconnections 525, 527 and also orthogonal to each otherthrough the conductive interconnections 521. In one embodiment, theexterior chips 560, 561, 562 are aligned, in a manner known in the art,prior to mounting to the base structure 525, and the module 550 is thenheated in an inert or reducing atmosphere to the melting point of thesolder used as connecting members.

[0029] The conductive interconnection 521 of the preferred embodimentallows for the exterior chips 560, 561, 562 to be interconnected to eachother for an increased I/O interconnection density, wherein an increasein the speed of the device is achieved by increasing the number ofavailable I/O interconnects. Another advantage gained is an increase inthe interconnection flexibility of the multichip structure, wherebyangled edge connections offer increased efficiency and performance ofthe multichip structural system. As such, the above-mentionedfabrication process significantly increases the I/O interconnect densityand the interconnect flexibility of multichip stacked structures. Aprocess and structure that allows solderable connections to be producedwith an increased I/O density and increased I/O interconnect flexibilityimproves the efficiency and the performance of a multichip stackedstructure.

[0030] Although the foregoing description of the various embodiments ofthe present invention have shown, described, and pointed out thefundamental novel features of the present invention, it will beunderstood that various omissions, substitutions, and changes in theform of the detail of the apparatus as illustrated as well as the usesthereof, may be made by those skilled in the art, without departing fromthe scope of the present invention. Consequently, the scope of thepresent invention should not be limited to the foregoing discussions,but should be defined by the appended claims.

What is claimed is:
 1. An integrated circuit module, comprising: a firstsemiconductor structure having a first surface defined by a first plane;a second semiconductor structure having a second surface defined by asecond plane, wherein the second structure is positioned adjacent thefirst structure in manner such that the second plane intersects thefirst plane; a first connecting member extending from the first surfaceof the first structure, the first connecting member having a firstdistal end electrically connected to the first surface and a seconddistal end extending from the first surface along a first axis; and asecond connecting member interposed between the second distal end of thefirst connecting member and the second surface of the second structure,wherein the second connecting member electrically interconnects thesecond distal end to the second surface and forms a bond therebetweenalong a second axis, wherein the second axis is not parallel to thefirst axis.
 2. The module of claim 1, wherein the second planeintersects the first plane at an approximately 90 degree angle.
 3. Themodule of claim 1, wherein the second plane intersects the first planeat an angle greater than 90 degrees.
 4. The module of claim 1, whereinthe second plane intersects with the first plane at an angle less than90 degrees.
 5. The module of claim 1, wherein the first connectingmember comprises a conductive pillar.
 6. The module of claim 5, whereinthe conductive pillar comprises copper.
 7. The module of claim 5,wherein the second connecting member comprises a solder ball.
 8. Themodule of claim 7, wherein the second connecting member comprises a C4structure.
 9. The module of claim 7, wherein the solder ball is formedon the second surface of the second semiconductor structure and extendsfrom the second surface along the second axis to make contact with thesecond distal end of the first connecting member.
 10. The module ofclaim 7, wherein the solder ball is formed on the second distal end ofthe first connecting member and extends from the second distal end alongthe second axis to make contact with the second surface of the secondsemiconductor structure.
 11. The module of claim 1, further comprising afirst conductive contact formed on the first surface of the firstsemiconductor structure, wherein the first distal end of the firstconnecting member is positioned adjacent to the first conductivecontact.
 12. The module of claim 11, wherein the first conductivecontact comprises a conductive pad.
 13. The module of claim 11, whereinthe first conductive contact comprises a conductive via.
 14. The moduleof claim 1, further comprising a second conductive contact formed on thesecond surface of the second semiconductor structure, wherein the secondconnecting member contacts the second conductive contact.
 15. The moduleof claim 14, wherein the second conductive contact comprises aconductive pad.
 16. The module of claim 15, wherein the secondconductive contact comprises a conductive via.
 17. The module of claim14, wherein the second connecting member comprises a conductive pillarhaving a first distal end positioned adjacent to the second conductivecontact and a second distal end extending from the second surface alongthe second axis.
 18. The module of claim 17, wherein the second distalend of the first connecting member and the second distal end of thesecond connecting member are joined together via a solder joint.
 19. Themodule of claim 18, wherein the first and second connecting members arejoined together at an approximately 90 degree angle.
 20. The module ofclaim 1, wherein the first semiconductor structure comprises anintegrated circuit chip.
 21. The module of claim 20, wherein the secondsemiconductor structure comprises an integrated circuit chip.
 22. Themodule of claim 21, wherein the integrated circuit structure is adaptedto be mounted to a multichip structure comprising a plurality ofintegrated circuit chips secured together in a stack.
 23. The module ofclaim 20, wherein the integrated circuit structure is mounted to a thirdintegrated circuit chip in a manner such that a first surface of thethird chip is positioned adjacent and substantially parallel to thesecond surface of the second chip, wherein the third chip iselectrically connected to the second surface via a plurality of soldercontacts formed between the second and third chips.
 24. A multichipmodule, comprising: a plurality of semiconductor chips stacked andsecured together to form a base structure wherein the base structure hasa first and a second lateral face, wherein each lateral face iscomprised of a portion of each chip, wherein the first lateral face isadjacent to and substantially perpendicular to the second lateral face;a first exterior semiconductor chip mounted to the first lateral face ofthe base structure in a manner such that a first surface of the firstexterior chip is positioned adjacent to the first lateral face andextends across at least a portion of the first lateral face; a secondexterior semiconductor chip mounted to the second lateral face of thebase structure in a manner such that a first surface of the secondexterior chip is positioned adjacent to the second lateral face andextends across at least a portion of the second lateral face; andwherein the first and second exterior chips are electricallyinterconnected via a connecting member, wherein the connecting membercomprises a first distal end electrically connected to the first surfaceof the first exterior chip and a second distal end electricallyconnected to the first surface of the second exterior chip.
 25. Themultichip module of claim 24, wherein the first distal end of theconnecting member extends along a first axis and the second distal endextends along a second axis, wherein the first axis and the second axisare non-parallel.
 26. The multichip module of claim 24, wherein thesecond distal end of the connecting member is joined to a solder ballformed on the first surface of the second exterior chip.
 27. Themultichip module of claim 26, wherein the connecting member comprises aconductive pillar.
 28. The multichip module of claim 24, wherein theconnecting member comprises a first and a second conductive pillar, afirst distal end of the first pillar extends from the first surface ofthe first exterior chip, a first distal end of the second pillar extendsfrom the first surface of the second exterior chip, a second distal endof the first pillar is electrically interconnected to the second distalend of the second pillar.
 29. The multichip module of claim 28, whereinthe first and second pillars are joined at an approximately 90 degreeangle.
 30. The multichip module of claim 28, wherein the first andsecond pillars are joined together by a solder joint.
 31. The multichipmodule of claim 24, wherein the first distal end of the connectingmember is positioned adjacent and electrically connected to a conductivecontact formed on the first surface of the first exterior chip.
 32. Themultichip module of claim 25, wherein the second distal end of theconnecting member is positioned adjacent and electrically connected to aconductive contact formed on the first surface of the second exteriorchip.
 33. A method of forming interconnection between two integratedcircuit structures, the method comprising: forming a first conductivecontact on a first surface of a first semiconductor structure and asecond conductive contact on a second surface of a second semiconductorstructure; forming a first connecting member on the first conductivecontact in a manner such that a distal end of the first connectingmember extends from the first surface of the first chip along a firstaxis; positioning the semiconductor chips in a manner such that theplane defining the first surface intersects with plane the defining thesecond surface; affixing a second connecting member to the distal end ofthe first connecting member; joining the second connecting member to thesecond conductive contact in a manner such that the second connectingmember is interposed between the distal end of the first connectingmember and the second surface of the second structure and forms a bondtherebetween along a second axis, wherein the second axis is notparallel to the first axis.
 34. The method of claim 33, wherein formingthe first connecting member comprises forming a conductive pillar. 35.The method of claim 34, wherein forming the first connecting membercomprises using a plating process.
 36. The method of claim 34, whereinforming the first connecting member comprises using a CVD process. 37.The method of claim 34, wherein forming the first connecting membercomprises using a blanket deposition in conjunction with a lift-offprocess.
 38. The method of claim 33, wherein forming the second contactcomprises forming a conductive pad.
 39. The method of claim 38, whereinforming the second connecting member comprises forming a solder ball.40. The method of claim 33, wherein forming the second contact comprisesforming a solder ball.
 41. The method of claim 33, wherein forming thesecond contact comprises using a lift-off process.
 42. The method ofclaim 41, wherein forming the second contact comprises using a tapeassisted lift-off process.
 43. The method of claim 33, wherein affixingthe second connecting member to the distal end of the first connectingmember comprises depositing solder on the distal end.
 44. The method ofclaim 43, wherein depositing solder on the distal end comprises using aselective immersion process.
 45. The method of claim 44, whereinaffixing the second connecting member to the distal end comprisesreflowing the solder in H₂ to form a solder ball.